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51	Lecture 5: More on Cache Memory William Gropp www.cs.illinois.edu/~wgropp Simplified Computer Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2015-01-15 10:20:46 Computer memory Computing Computer architecture Computer hardware Cache Computer engineering Central processing unit CPU cache Memory hierarchy Random-access memory Draft:Cache memory Scratchpad memory
52	High-performance matrix-matrix multiplications of very small matrices I. Masliah2 , A. Abdelfattah1 , A. Haidar1 , S. Tomov1 , M. Baboulin2 , J. Falcou2 , and J. Dongarra1,3 1 Add to Reading List Source URL: icl.cs.utk.edu Language: English - Date: 2016-06-07 14:32:34 Computing Computer architecture Computer hardware Parallel computing GPGPU Numerical linear algebra Numerical software Cache Basic Linear Algebra Subprograms CPU cache Multi-core processor Graphics processing unit
53	Performance Characteristics of the POWER8™ Processor Alex Mericas Systems Performance IBM Systems & Technology Group Development Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2014-08-15 19:04:06 Computer architecture Computing POWER8 POWER7 CPU cache Intel Core PowerPC 400 Xeon
54	Adaptive Line Placement with the Set Balancing Cache Dyer Rolán Basilio B. Fraguela Ramón Doallo Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2009-09-04 07:55:51 Cache Computer architecture Computer memory Central processing unit CPU cache Cache algorithms Memory hierarchy Lookup table Saturation arithmetic Draft:Cache memory
55	Power-Aware Memory Management © 2003, Carla Schlatter Ellis ESSES 2003 Add to Reading List Source URL: www.cs.duke.edu Language: English - Date: 2003-08-21 10:16:22 Computer memory Dynamic random-access memory Random-access memory Rambus Memory controller CPU cache RDRAM
56	Godson-2E software manual Contents 1 Godson-2E Micro Architecture...................................................................................1 1.1 Godson Series Processors ........................................ Add to Reading List Source URL: dev.lemote.com Language: English - Date: 2011-05-04 12:04:52 Central processing unit CPU cache Translation lookaside buffer Loongson Processor register Control register Instruction set Addressing mode MIPS instruction set Draft:Cache memory
57	Parallel Computing–248 www.elsevier.com/locate/parco A compiler tool to predict memory hierarchy performance of scientiﬁc codes q B.B. Fraguela a, R. Doallo Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2004-03-17 11:53:46 Cache Compiler optimizations Computer memory Computer architecture Software optimization CPU cache Optimizing compiler Locality of reference Automatic parallelization Infinite loop Memory hierarchy Lookup table
58	Design of Parallel and High-Performance Computing Fall 2014 Lecture: Cache Coherence & Memory Models Instructor: Torsten Hoefler & Markus Püschel Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-10-12 15:57:01 Computer architecture Computer memory Cache coherency Concurrent computing Parallel computing Cache Random-access memory Shared memory CPU cache Memory hierarchy
59	Faster Fourier Transforms via Automatic Program Specialization Julia L. Lawall IRISA { Compose group Campus Universitaire de BeaulieuRennes Cedex, France Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:05:17 Digital signal processing Cache Computer memory Compiler optimizations Algorithms Divide and conquer algorithms Fast Fourier transform CPU cache Optimizing compiler Partial evaluation Speedup Template
60	Performance Portable Optimizations for Loops Containing Communication Operations Costin Iancu Wei Chen, Katherine Yelick Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-10-24 14:33:15 Compiler optimizations Loop optimization Automatic parallelization Loop nest optimization CPU cache Program optimization Software pipelining Lookup table Distributed computing Fortran Compiler Algorithm

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